Designed FIR filter with multiple constant multiplication. Unfortunately gives correct answer only on first clk. Since the fist answer is correct i guess the problem is at bottom adders and flipplops but i cant find the solution. working on more than 10 hours:(. plz help~ input : 12bit unsigned ... my iir filter in verilog hdl. Contribute to dustcat/IIR_m development by creating an account on GitHub.